1. Field of the Invention
The present invention generally relates to PCI-X (Peripheral Component Interconnect-X) bridges, and more particularly to performance of PCI-X bridges in forwarding split completion data.
2. Description of the Related Art
In a conventional computer system, a PCI-X bridge couples a first bus to a second bus. The first bus may be a PCI-X bus, a PCI bus, or a Front Side Bus (FSB). The second bus may be a PCI-X bus or a PCI bus. The first bus is a FSB if it is coupled to at least a processor. In that case, the PCI-X bridge is called a Host/PCI-X bridge.
Assume the PCI-X bridge in the conventional computer system couples a first PCI-X bus to a second PCI-X bus. Assume further that a first PCI-X device and a second PCI-X device reside on the first and second PCI-X buses, respectively. Assume further that the first PCI-X device on the first PCI-X bus initiates a block read transaction to read data from the second PCI-X device on the second PCI-X bus. Because the first and second PCI-X devices must communicate via the PCI-X bridge, the transaction must be carried out as a split transaction. A split transaction consists of a request by a requester followed by a completion by a completer at a later time.
As a requester, the first PCI-X device sends a read request to the PCI-X bridge via the first PCI-X bus. The read request is called a split read request. The PCI-X bridge responds by sending back a split read response to the first PCI-X device on the first PCI-X bus. The PCI-X bridge then reinitiates the split read request to the second PCI-X device via the second PCI-X bus. Assume the second PCI-X device needs time to gather the requested data from its memory, the second PCI-X device responds to the split read request from the PCI-X bridge by sending back a split read response to the PCI-X bridge. At a later time, when the second PCI-X device has gathered all the requested data (called split completion data), the second PCI-X device sends the split completion data to the PCI-X bridge via the second PCI-X bus. Finally, the PCI-X bridge sends the split completion data to the first PCI-X device via the first PCI-X bus.
The mechanism used by the PCI-X bridge to forward the split completion data to the first PCI-X device on the first PCI-X bus has a large impact on the efficiency and latency of the computer system. Latency is defined as the time period from the time a data item is sent from a source to the time the data item is received at a destination. Efficiency of a system can be defined as how well the system's resources are used. A system operating with high efficiency means that a high percentage of the system's resources are used for the ultimate purposes of those resources, and without unnecessary overhead. For example, in the case of a bus, the system operates with high efficiency if a high percentage of the bus bandwidth is used for transferring data (which is the ultimate purpose of a bus). If a large percentage of the bus bandwidth is not used for transferring data (for instance, the bus is idle), the system operates with low efficiency. However, efficiency and latency are two competing goals in conventional computer systems.
Assume, in a first scenario, that the PCI-X bridge delivers split completion data from the second PCI-X device to the first PCI-X device only when the PCI-X bridge receives all the split completion data from the second PCI-X device. In this case, high efficiency can be achieved because the PCI-X bridge can forward all the split completion data to the first PCI-X device in one burst (i.e., no bus idling occurs from the beginning to the end of the forwarding of all the split completion data). However, a drawback is high latency because the first split completion data item must wait for the last split completion data item to come to the PCI-X bridge before the first split completion data item is delivered to the first PCI-X device on the first PCI-X bus.
Assume alternatively, in a second scenario, that the PCI-X bridge delivers split completion data from the second PCI-X device to the first PCI-X device when the PCI-X bridge receives less than all the split completion data from the second PCI-X device. In this case, lower latency is achieved compared with the case in the first scenario. However, a drawback is lower efficiency because the PCI-X bridge may run out of split completion data and has to disconnect at the next ADB (Allowable Disconnect Boundary). At a later time, when the PCI-X bridge receives more split completion data from the second PCI-X device, the PCI-X bridge delivers the next burst of split completion data to the first PCI-X device. Therefore, the PCI-X bridge may have to forward the split completion data to the first PCI-X device in one or more bursts with the first PCI-X bus being idle between these bursts, resulting in lower efficiency.
Accordingly, there is a need for an apparatus and method in which a PCI-X bridge forwards split completion data from one PCI-X device to another with relatively low latency and relatively high efficiency.